This application claims priority from European App""n 93830159.5, filed Apr. 9, 1993, which is hereby incorporated by reference.
The present invention relates to output power stages employing a power switch for connecting to a ground node a load and wherein static power consumption within the driving circuit is substantially eliminated.
A circuit for switchingly connecting to ground (low-side driver) an external load employing a power switch has a basic diagram as shown in FIG. 1.
Commonly the power switch Pw is a transistor, and often an integrated DMOS transistor (which offers definite advantages over a bipolar junction transistor). The integrated transistor structure intrinsically contains a junction (diode) Dr through which, in case of reactive loads, transient currents may recirculate. The power transistor Pw constitutes the output stage and is controlled by a driving circuit which determines a state of conduction or of nonconduction of the transistor, according to a certain xe2x80x9cduty cyclexe2x80x9d (in most applications).
In this way, an output signal having an amplitude comprised between V1=Rdson*Id and Vh=H.V. is produced, where H.V. is the supply voltage to which the external load is connected, Rdson is the saturation resistance of the power transistor Pw, and Id is the current through the load.
In order to ensure a low voltage drop through the power transistor Pw when it is conducting, and therefore a low power dissipation, it is highly desirable to minimize the Rdson value. This is achieved by driving the power transistor with a (gate) voltage that is higher than the voltage that is necessary for switching-on the transistor. Normally, for a DMOS transistor such an overdrive voltage may reach about 10V, i.e. Vgs=10V, that may be equal to the supply voltage Vcc of the control circuit.
Moreover, the output signal (OUT) is often required to have certain slew-rate characteristics (Tf and Tr) and delays (TPHL and TPLH), as referred to the control signal (IN), controlled and equal to each other, as depicted in FIG. 2.
On the other hand, in order to switch-on the power transistor Pw, it is necessary to charge the capacitance of the driving node (gate node) up to a voltage that is higher than the threshold voltage Vth of the transistor. If, during a switch-on phase, driving is effected through a constant current generator I1 driven by the switching signal IN (FIG. 1), the gate voltage will have a diagram versus time as the one depicted in FIG. 3. Three different zones of operation of the power transistor may be distinguished, as determined by the actual input capacitance that varies from zone to zone.
In a first zone I of the characteristic, the gate voltage rises from Vgs=0V to Vgs=Vth. In this interval of time no current flows through the power transistor which remains in an off condition. The interval t0-t1 is defined as turn-on delay time TPHL. After the instant t1, the power transistor starts to conduct and the voltage Vds across the power transistor drops from Vh to Vdson=V1.
In a zone II of the characteristic, normally referred to as the saturation zone, the ratio xcex94Vds/xcex94Vgs is high and therefore the Miller effect becomes preponderant in determining the input capacitance as compared with the xe2x80x9cphysicalxe2x80x9d gate capacitance of the power transistor. Because of this, the driving current primarily charges the xe2x80x9cMillerxe2x80x9d capacitance while a negligible portion of it charges the Cgs capacitance between gate and source of the power transistor Pw, thus causing a negligible variation of the Vgs voltage. In fact, the gate voltage rises from the value Vgs=Vth to the value Vgs=Vs (Vs is also referred to as the operative voltage). The interval t1-t2 is defined as the fall time Tf.
In the zone III of operation, the gate capacitance charges completely to the voltage Vcc and the power transistor is fully on (low internal resistance).
Similarly, for switching-off the power transistor Pw, its gate capacitance is discharged through a constant current generator I2, which is functionally connected between the gate node of thee power transistor and ground and which is driven by a switching signal IN, in opposite phase with respect to the switch signal IN driving I1. During a xe2x80x9ctime offxe2x80x9d phase phenomena similar to those that occur during the xe2x80x9cturn-onxe2x80x9d phase takes place, as depicted in FIG. 4. Also in this phase of operation in fact, the gate capacitance discharges through three distinct phases.
In a first phase or zone I of the characteristic, the gate voltage drops from the value Vgs=Vcc to the operative voltage Vgs=Vs, while the drain voltage remains at Vdson. This interval (txe2x80x20-txe2x80x21) is defined as the turn-off delay time TPLH.
In a second region II of the characteristic, the voltage Vgs drops from Vs to the threshold voltage Vth and during this phase the power transistor Pw starts to carry less and less current until it switches-off completely. The duration of this interval (txe2x80x21-txe2x80x22) during which the drain voltage rises from V1 to Vh, is defined as the rise time Tr.
If the currents I1 and I2 have the same value, the rise time and the fall time are identical.
In order to have a large charge current (Ic) and a large discharge current (Is) of the gate capacitance of the power transistor Pw for achieving fast switching times, while employing control current generators I1 and I2 of relatively low value, a driving circuit as the one depicted in FIG. 5 is employed. In fact, the relationship that ties the currents Ic and Is to the currents ID1 and ID4 is of an exponential kind:
Ic=n*ID1 exp R*ID1/Vt
Is=n*ID4 exp R*ID4/Vt
If ID1 and ID4 are equal, the currents Ic and Is will be equal and so also the fall time and the rise time.
In practice, in a circuit as the one depicted in FIG. 5, the current ID4 is different from ID1. In fact, the MOS M1 and M2 operate with a constant Vgs, therefore the current ID1=I, while the MOS M3 and M4 operates with a Vgs that varies because their source is not connected to a fixed voltage, but to the gate of the power transistor Pw, the voltage of which drops during a turn-off phase. Therefore, ID4xe2x89xa0I.
Commonly, in order to obviate to this drawback, the sources of M3 and M4 are connected to a fixed voltage, for example to the supply voltage Vcc, so that, the current mirror formed by M3-M4, generates the same current as the current mirror M1-M2. Such a known solution is depicted in FIG. 6, and a functional block diagram may be depicted as in FIG. 7.
In this circuit, the transistors M2 and M4 do not exactly operate under the same conditions. In fact, M4 operates always in a saturation zone, with Vgs1=constant and Vds1=constant=Vccxe2x88x922Vbe, and the transistor M2 operates in a saturation zone until Vds2=Vgs2-Vth and thereafter operates in a linear zone. When M2 operates in a linear zone, the gate voltage of the power transistor Pw has already risen, above the operative voltage Vs, therefore the transistor no longer operates in the zone II and therefore the drain of the transistor has already assumed the voltage Vh.
This circuit has a drawback represented by the fact that when the power transistor Pw is off, and therefore its gate voltage is Vgs=0V, a certain current consumption (drawn from the supply line Vcc) occurs and is given by the sum: I2+ID4.
In integrated circuits where numerous driving stages of this type are present, such a static current consumption may reach intolerable levels.
A main objective of the invention is to provide an improved control circuit for a low-side driver stage that without penalizing speed and precision characteristics has a substantially null static current consumption.
This objective is reached with the driver circuit of the present invention, which is characterized by the presence of a switch capable of preventing any flow of current through the discharge current generator of the control node capacitance of the power transistor, when the latter is in an off state. Such a switch is controlled by the voltage present on the control node of the power transistor. In practice, the driving circuit of the invention has a null static consumption when the power transistor is off and an extremely low consumption which would be practically negligible, when the power transistor is on.